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IP Core Library

Reuse known-good cores instead of asking for the same block to be written again.

The best RTL is often RTL you do not write. With the IP Core Library on, a run first checks a catalog of known-good cores and uses a match if there is one, rather than reinventing the block from your description.

What it does

IP Core Library allows the generator to consider existing Xilinx IP cores rather than implementing every function from scratch in RTL. When a suitable verified core covers what you asked for, the platform can recommend or integrate that IP into the generated architecture. That reduces the amount of new code you have to review, and lets the design take advantage of implementations already optimised for Xilinx FPGA families.

If nothing in the catalog fits your request, the run carries on exactly as it would have with the switch off. Turning it on never blocks a run; the worst case is that it finds nothing and costs a few seconds.

When it pays off

Best used for:

  • PCIe, Ethernet, DDR, and other complex interfaces
  • High-performance arithmetic blocks
  • Designs where timing or resource efficiency is important

Example

Instead of generating a large asynchronous FIFO entirely from RTL, the design may use the FPGA vendor's dedicated FIFO implementation when appropriate.

It also earns its keep on the everyday blocks:

  • Standard peripherals. UARTs, SPI masters, I2C controllers, PWM generators; blocks with a settled, well-understood shape.
  • Bus infrastructure. Interconnect, bridges, register files.
  • Common datapath elements. FIFOs, CDC synchronisers, CRC units.

And when it does not:

  • Anything genuinely specific to your design; there is nothing in a catalog to match.
  • Blocks where you care more about matching your own conventions than about reuse.
  • VHDL output, where the switch is unavailable.

Reviewing a reused core

A reused core is still your responsibility. Read it the way you would read anything from an external source:

  • Check the reset style against the rest of your design.
  • Check the parameter defaults; a core built for 8 bits will happily be instantiated at 8 bits.
  • Run the testbench. Auto-Verify covers reused cores as well as generated ones.